Program Detailed Schedule
19th December 2011 (Monday) – ISED (Venue: Ramada Resort Cochin)
08:30AM -- 09:30AM	Registration, Light Breakfast
09:30AM --10:30AM	ISED Inaugural Event Prayer, Steering Committee Chair -- 5mins, General Chair – 10mins, Program Chair – 10mins, and Remaining time TBD.							Registration
10:30AM -- 11:15AM	Plenary Talk Title: Design and Methodology Challenges in Next generation SoC Development Abstract: As semiconductor technology approaches scaling limits the next generation SOCs can no longer assume cost reduction from scaling as a given. It is also not obvious that monolithic integration will in fact drive costs down as it has for semiconductor technology for the last four decades. Disintegration not integration may be the path to lower the cost of next generation SOCs. Is traditional worst case design still the best way to produce reliable performance at the lowest cost? High levels of parametric variations in nanometre processes require investment of significant silicon real estate to overcome the consequences of variability. If one were to design for the mean and use the “saved” silicon real estate to incorporate calibration and configurability circuitry it seems possible that one would discover improved optimization. Self or assisted test and on-chip calibration should make it possible to reduce cost of test by adoption of iterative, experimental and statistical methods. An introduction to the challenges and some approaches towards suitable methodologies will be discussed Biography: Rajat Gupta is an Independent Consultant, India. Rajat obtained his B.E. in Electronics and Tele-communications from Calcutta University in 1980 and an M.Tech in Integrated Electronics and Circuits from IIT, Delhi in 1982. He holds four US patents and is a senior member of IEEE.
11:15AM --12:30PM	Analog/Mixed-Signal System Design (AMS) – 1 Session Chair: Dr. Babita Roslind Jose, CUSAT			Digital System Design and Validation (DSD) – 1 Session Chair: Dr. Saraju Mohanty, UNT			Software System and Application Design (SSD) – 1 Session Chair: Dr. Ranjani Narayan, Morphing Machines
12:30PM -- 01:30PM	Lunch
01:30PM -- 02:00PM	Plenary Talk Title: Digital PID Control Design: A Data Based Approach Abstract: In this talk we describe recent results in the design of Proportional Integral Derivative (PID) controllers that are implemented digitally. These results emphasize a data based approach as opposed to a model based one. It is shown that measurement data from the system can be directly used to obtain the complete set of PID controllers in a computationally efficient manner. The problem of searching for controllers achieving multiple design specifications within this set, can also be solved in a computationally efficient manner. Since the methods employed use the raw measurement data rather than a model constructed from these it is an attractive new approach. Examples will be included to illustrate the results. Biography: Shankar P. Bhattacharyya, Texas A & M University Shankar P. Bhattacharyya is the Robert M. Kennedy Professor of Electrical Engineering at Texas A & M  University. He was educated at IIT Bombay (B.Tech, 1967), and Rice University (MS, 1969, Ph.D 1971). His research interests include Robust Control and Control System Synthesis and he has 7 books and nearly 250 journal and conference publications detailing several fundamental contributions to the field. He has held a Senior Fullbright Lecturership, a NASA-NRC Research Associateship, a Boeing-Welliver Fellowship and. Senior TEES Fellowship. He is a Fellow of the IEEE and a Fellow of the IFAC.
02:00PM -- 03:15PM	Analog/Mixed-Signal System Design (AMS) – 2 Session Chair: Dr. Dipankar (email:Dipankar@treelabs.org)			Digital System Design and Validation (DSD) – 2 Session Chair: Prof. S.K Nandy, IISc			Software System and Application Design (SSD) – 2 Session Chair: Dr. Rajat Gupta
03:15PM -- 3:45PM	Tea break
3:45PM -- 4:15PM	Plenary Talk Title: Reconfigurable Silicon Cores - Opportunities and Challenges Abstract: Embedded Systems of the future have to address the big challenge of delivering high performance at very low energy budgets. This translates into reusing hardware and provisioning “hardware on demand”.  Reconfigurable Silicon cores on a single chip has the potential to serve as the hardware infrastructure from which Custom Silicon cores/IPs can be composed and deployed on demand. Temporal and spatial reuse and redeployment of hardware resources is key to meet the power-performance requirements. In this presentation, we will discuss the opportunities and challenges associated with such Reconfigurable Silicon Cores in Electronics System Design. Biography: Ranjani Narayan, Morphing Machines, India Ranjani Narayan is the CTO of Morphing Machines, Pvt Ltd, a semiconductor startup engaged in the design, development and deployment of Reconfigurable Silicon Cores. She obtained her PhD from the Indian Institute of Science in 1989, and BE (Hons) from the Indian Institute of Science in 1980.  Prior to joining Morphing Machines, she worked in Hewlett Packard as an Architect and has several years of experience in OS, System Diagnostics, and Self Healing Systems. She has many publications in Journals and proceedings of International Conferences to her credit.  Her research interests include Processor Architectures, Heterogeneous Multi-cores Architectures, Embedded SoCs and Reconfigurable Silicon Cores.
4:15PM -- 5:30PM	Analog/Mixed-Signal System Design (AMS) – 3 Session Chair: Rohit Khanna.			Digital System Design and Validation (DSD) – 3 Session Chair: : Prof. D. K. Das , Calcutta			Software System and Application Design (SSD) – 3 Session Chair: Dr.  Chandan Haldar
5:30PM -- 7:00PM	Networking
	Break
7:00PM -- 9:00PM	Cultural Programs				Symposium Banquet
20th December 2011 (Tuesday) – ISED (Venue: Ramada Resort Cochin)
09:00AM -- 10:00AM	Registration, Light Breakfast
10:00AM -- 11:15AM	Emerging Technology and System Design   (ETD) – 1 Session Chair: Prof. Bhargab  Bhattacharya , ISI		Digital System Design and Validation (DSD) – 4 Session Chair: Dr. Smitha K.G, NTU, Singapore			Embedded System Design (ESD) – 1 Session Chair: Dr. Samrat Sabat
11:15AM -- 11:45AM	Plenary Talk Title: Architecture and Design Issues for 3D ICs – a Tera‐scale Perspective Abstract: TSV-based 3D chip stacking and integration technology was proposed more than twelve years ago. Since then the concept has gained tremendous traction with significant advances in the technology, computer-aided design and system architectures. Today, multiple foundries offer a TSV process for 3DICs. Many design teams in academia and industry have been working towards a convincing 3D prototype that will demonstrate form factor reduction, heterogeneous integration and higher performance. However, the commercial success of true 3DICs has been limited to DRAM stacking. This presentation will introduce technology scaling trends and new challenges. We are at an I/O inflection point due to Tera-scale computing needs. 3DICs provide an excellent alternative to address the memory bandwidth issue by providing a large near-processor memory. In this presentation we will discuss architecture, and floorplanning challenges in large 3DIC prototypes. The presentation will include with a discussion on test, power delivery and thermal management issues related to 3D integration. Intel Lab’s Academic Research Office is investing in 3DIC research to bring the 3D research concepts to fruition. The main objective is to build a convincing prototype including heterogeneous processors and heterogeneous memories to demonstrate a superior power/performance trade-off along with form factor reduction. This presentation will include the recent developments in the research program on 3DICs for tick tock model enhancement. Biography: Tanay Karnik,     Intel Research, USA Tanay Karnik is a Principal Engineer and Program Director in Intel Lab’s Academic Research Office. He received his Ph.D. in Computer Engineering from the University of Illinois at Urbana-Champaign in 1995. His research interests are in the areas of variation tolerance, power delivery, soft errors and physical design. He has published over 45 technical papers, has 44 issued and 33 pending patents in these areas. He received an Intel Achievement Award for the pioneering work on integrated power delivery. He was a member of ISSCC, DAC, ICCAD, ICICDT and ISQED program committees and JSSC, TCAD, TVLSI, TCAS review committees. Tanay was the General Chair of ASQED’10, ISQED'08, ISQED'09 and ICICDT'08. Tanay is IEEE Senior Member, ISQED Fellow, Associate Editor for TVLSI and Guest Editor for JSSC.
11:45AM – 12.30PM	Plenary Talk Title: CMOS Reliability: Trends and Design Techniques Abstract: In nanometer-scale CMOS technologies, reliability issues are projected to become a major problem and must be taken into account during circuit design. While there has been tremendous progress in developing enhanced methods for modeling and diagnosing reliability at the individual transistor level, there has been much less work that propagates these models to higher levels of abstraction and creates an infrastructure to predict the reliability of larger circuits.  This talk will discuss the roots of the problem, and sources of reliability degradation due to phenomena such as bias temperature instability, oxide breakdown, and hot carrier effects.  It will then overview research to develop new computer-aided design techniques for analyzing and enhancing the reliability of large logic circuits.  Finally, it will conclude by presenting directions for future research. Biography: Sachin Sapatnekar, University of Minnesota Sachin S. Sapatnekar received his B. Tech. from IIT Bombay, M.S. from Syracuse Univ., and Ph.D. from the Univ. of Illinois at Urbana-Champaign.  He holds the Distinguished McKnight University Professorship and the Henle Chair Professorship at the University of Minnesota. His research is related to developing CAD techniques for the analysis and optimization of circuit performance. He has served as General Chair for the ACM/IEEE Design Automation Conference (DAC) and is currently Editor-in-Chief of the IEEE Transactions on CAD. He is a recipient of six Best Paper awards, and the SRC Technical Excellence award. He is a fellow of the IEEE.
12:30PM -- 01:30PM	Lunch
01:30PM -- 02:45PM	Emerging Technology and System Design   (ETD) – 2 Session Chair: Dr. Narayan Komerath, Gatech.		Power-Aware System Design (PSD) – 1 Session Chair: Prof. Jacob Abraham, The University of Texas at Austin			Embedded System Design (ESD) – 2 Session Chair: Dr. Hafizur Rahaman
02:45PM -- 03:30PM	Plenary Talk Title: Exploiting Unreliable Memories Abstract: While designers have traditionally dealt with unreliableembedded memories through standard fault-tolerant techniques in the past, aggressive technology scaling and low voltage operation (to save power) pose significant reliability challenges for distributed embedded memories. In this paper,we survey a series of hardware and software schemes that both ameliorate poor reliability, and exploit unreliable embedded memories through hardware and software mechanisms in order to achieve a low-power, fault-tolerant memory space, and keep production yield at tolerable levels. We outline techniques such as voltage scaling, block re-mapping, and device signatures to deal with process variations and reduce power consumption. We explore the benefits/drawbacks of various schemes and motivate the need for, and present E-RoC, a holistic hardware/software solution that virtualizes the user memory space and exploits unreliable distributed embedded memories for reduced power consumption. Biography: Nikil Dutt, University of California, Irvine Received the Ph.D. degree in computer science from the University of Illinois at Urbana-Champaign, Urbana-Champaign, in 1989.He is currently a Chancellor’s Professor with the University of California, Irvine, with academic appointments in the Computer Science and Electrical Engineering and Computer Science Departments. His research interests include embedded systems, electronic design automation, computer architecture, optimizing compilers, system specification techniques, and distributed embedded systems. Prof. Dutt was a recipient of Best Paper Awards from CHDL89, CHDL91, VLSIDesign2003, CODES+ISSS 2003, CNCC 2006, and ASPDAC-2006. He currently serves as Editor-in-Chief of the ACM Transactions on Design Automation of Electronic Systems (TODAES) and as an Associate Editor of the ACM Transactions on Embedded Computer Systems (TECS) and of the IEEE Trans. On VLSI Systems (T-VLSI). He was an ACM SIGDA Distinguished Lecturer during 2001–2002, and an IEEE Computer Society Distinguished Visitor for 2003–2005. He has served on the steering, organizing, and program committees of several premier CAD and Embedded System Design conferences and workshops, including ASPDAC, CASES, CODES+ISSS, DATE, ICCAD, ISLPED, and LCTES. He serves or has served on the advisory boards of ACM SIGBED and ACM SIGDA, and IFIP WG 10.5. He is an ACM Distinguished Scientist and an IFIP Silver Core Awardee.
03:30PM -- 04:00PM	Tea break
04:00PM -- 05:15PM	Emerging Technology and System Design   (ETD) – 3 Session Chair: Jimson Mathew, U. of Brsito, UK	Power-Aware System Design (PSD) – 2 Session Chair: Dr. Mahadevan Gomathisankaran, UNT				ISED Committee Meeting
05:15PM -- 05:45PM	Plenary Talk Title: Securing Embedded Systems – Catching the Ghost in the Machine Abstract: Ever expanding capabilities, features, and complexity of the current generation of mission-critical embedded systems are leading to integration of trusted and untrusted modules within integrated execution environments – both in the hardware and in the software layers.  Secure application execution and robust data protection in such potentially unsafe integrated environments pose new architectural and design challenges.  Security strategies conventionally used for protection of systems and applications against external attacks are ineffective in adequately addressing the security needs of modern mission-critical embedded systems whose execution environments potentially have internal sources of security threats.  In this talk, we explore the use of reference monitors and related techniques in security framework architectures for such environments. Biography: Chandan Haldar, Morphing Machines, India Dr. Chandan Haldar is the Managing Director of Morphing Machines Pvt Ltd, a semiconductor start-up launched from the Indian Institute of Science at Bangalore focused on reconfigurable silicon cores for high-performance solutions in multi-protocol cryptography, video and image processing, avionics guidance and control, and software defined radio.  He is also Chairman and Chief Scientist at Terra Incognitus Systems Research Alliance Pvt Ltd (TISRA), a company that uses research-centric advanced computing technologies to create simple and effective breakthrough open software solutions focused on problems relevant to the needs of India and other emerging markets.  Dr. Haldar was the founder Director and head of the Lucent Technologies INS India Development Center and held Senior Director positions at America Online and Electronics for Imaging.  Earlier he held various technical and managerial roles at Siemens and Sun Microsystems.  Recently he has been associated with several technology start-ups.  He earned his B. Tech (Honors) and M. Tech degrees at the Indian Institute of Technology at Kharagpur and his Ph. D. degree at the Indian Institute of Science at Bangalore.  He is an alumnus of the Senior Executive Programme at the London Business School as Aditya Birla Scholar, and a Senior Member of the ACM, IEEE, and IEEE Computer Society.
05:45PM -- 06:30PM	Networking

21st December 2011 (Wednesday) – WES Celebrating Women in Engineering (Venue: Rajagiri School of Engineering & Technology Campus)
09:00AM - 10:00AM	WES Inauguration RSET Dignitaries, and ISED General and Workshop Chairs.	Registration, Light Breakfast
10:00AM – 11:00AM	Plenary Talk Title: Beyond Moore’s Law Technologies & Architectures Abstract: Conventional shrinking methods to improve VLSI chip performance by continual scaling of device and interconnect geometries may allow CMOS juggernaut to reach about 22 nm nodes. During the post- shrinking era, a host of nanoscale technologies such as quantum tunneling devices, plasmon based transistors, ionic transport based crossbar structures, carbon nano-tube FET’s, grapheme FET’s, self- assembled array of quantum dots, spin-polarized magnetic tunneling junction devices, and molecular transistors are likely to emerge as commercially viable technologies that will sustain the demands for exponential economic growth throughout the present millennium. Quantum tunneling in nanometric devices augurs a revolutionary shift of paradigm for circuit and CAD tools design that must account for quantum effects as well as local interactions between self- assembled circuit elements. These circuit elements may consist of a 2-dimensional array of self-organized quantum dots that can be instrumented to perform cellular automata class of algorithms or a 3-dimensional array of self-organized nanowires to perform a random Boolean network (RBN) class of algorithms. The talk will briefly introduce several Boolean and neuromorphic nanoarchitectures consisting of 2-D array of amorphous-Silicon based memristor devices, stress-assisted spin polarized nanomagnets, and surface plasmon polariton (SPP) based THz active and passive devices. Biography: Pinaki Mazumder, University of Michigan, Ann Arbor Professor Mazumder received his Ph. D. in Electrical and Computer Engineering from the University of Illinois at Urbana-Champaign in 1988. Prior to that, he received his M. S. degree in Computer Science from University of Alberta in Canada, B. S. degree in Electrical Engineering from Indian Institute of Science at Bangalore, and B. Sc. Physics Honors degree from Guwahati University in India. Currently, he is a Professor of Electrical Engineering and Computer Science at the University of Michigan where he has been teaching for the past 24 years. He spent three years at National Science Foundation serving as the lead Program Director of Emerging Technologies Program in the CISE Directorate as well as leading the Quantum, Molecular, and High Performance Simulation Program in the Engineering Directorate. He had worked for six years in industrial R&D laboratories which included AT&T Bell Laboratories, where he started the first C language based modeling techniques for VLSI synthesis tool in 1985. Prof. Mazumder spent his sabbatical at Stanford University, University of California at Berkeley, and NTT Center Research Laboratory in Japan. He has published over 250 technical papers and 4 books on various aspects of VLSI technology and systems. His research interest includes CMOS VLSI design, semiconductor memory systems, CAD tools and circuit designs for emerging technologies including quantum MOS, spintronics, plasmonics, and resonant tunneling devices. Prof. Mazumder was a recipient of Digital's Incentives for Excellence Award, BF Goodrich National Collegiate Invention Award, DARPA Research Excellence Award, and IEEE Distinguished Lecturer. Prof. Mazumder is an AAAS Fellow (2007) and an IEEE Fellow (1999).
11:00AM -- 11:45AM	WES Invited Talk Title: Invent the Inventor, Create the Entrepreneur - The TreeLabs perspective in energy-efficient engineering Abstract: The business of energy efficiency is a major game changer and not mere rhetorical elegance. Almost everything we use in our daily lives are hugely energy inefficient - lights, fans, pumps, etc. For example, the average ceiling fan works at a mere 1-2% efficiency. This legacy must and can be changed. The ability to trigger our inventive engineering instincts, and backing it up with rock-solid support, can lead to a revolution to make our Earth green again. TreeLabs is a Gun/Linux-like movement to enable inventions leading to enterprise. Biography: Dipankar, TreeLabs B.Tech(EE) from IIT-Bombay ('84-'88). Masters and PhD in Physics from Rice University (Houston, TX). Did pioneering work in experimental physics, in various areas like Scanning Probe Microscopy, Buckyballs,  Femto-second lasers, etc. Ph. D. involved solving the Maxwell equations exactly, analytically. Published in reputed journals like Science, PRL, Physical Review, etc. Techno-entrepreneur since high-school. Founded a high-tech R&D company (Angstrom) immediately after completion of PhD. Founder of an international NGO called FOYM (US and India based) dedicated to education of the underprivileged. Teaching and guiding students at IIT-Bombay (electronics) for more than ten years. At present involved in creating TreeLabs (www.treelabs.org), a global movement in the commons.
11:45AM – 12:30PM	WES Invited Talk Title: The joys and perils of a research career: my journey so far Abstract: I will talk about my personal experiences in research and academia as well as the perspectives I have gained from others. I plan to provide the audience with an insider view that will hopefully help them make an informed decision on choosing a research career. I believe that a career in research can be highly rewarding under the right circumstances. Biography: Animashree Anandkumar, University of California, Irvine Anima Anandkumar has been a faculty at the EECS Dept. at University of California, Irvine since Aug. 2010. She was previously at the Stochastic Systems Group at MIT as a post-doctoral researcher. She received her B.Tech in Electrical Engineering from IIT Madras in 2004 and her PhD from Cornell University in 2009.  She is the recipient of the 2011 ACM Sigmetrics Best Paper Award, 2009 ACM Sigmetrics Best Thesis Award, 2008 IEEE Signal Processing Society Young Author Best Paper Award, and 2008 IBM Fran Allen PhD fellowship. Her research interests are in the area of high-dimensional statistics, networking and information theory with a focus on probabilistic graphical models.
12:30PM -- 01:30PM	Lunch
01:30PM -- 02:45PM	WES Invited Talk Title: Photonics Research at IIT Madras Abstract: The Photonics group at IIT Madras started about 8 years ago with three faculty members. The group now has eight members who work in photonics as well as collaborate actively with the VLSI & Microelectronics group. In addition, work is carried out along with other faculty like those from the communications and instrumentation groups.  The Photonics group works on a wide range of activities comprising Optical Communication/Networking, Metrology, Components (e.g. diffractive optics, optical MEMS, fiber optics sensors), Computational Electromagnetics, Plasmonics, Nonlinear Optics, Silicon Photonics and Integrated Optics and Fiber Lasers. The talk will consist of two parts. Initially, I will give an overview of the work done in the group and then follow it up by discussing one particular application and its importance in detail. Biography: Shanti Bhattacharya, Indian Institute of Technology, Madras Shanti Bhattacharya obtained her Ph.D in Physics from the Indian Institute of Technology, Madras in 1997. Her Ph.D work was in the area of Optical Array Illuminators. She was awarded the Alexander von Humboldt award in 1998 and spent more than two years at the Technical University of Darmstadt, Germany. Her research work there included development of an optical pick-up for CD/DVD systems and design of diffractive optical elements for beam shaping of high power laser beams. She subsequently joined the MEMS division of Analog Devices, Cambridge, USA. She is currently an Associate Professor and has been with the Department of Electrical Engineering, IIT Madras since 2005. Her current research interests are optical MEMS, diffractive optics and fibre interferometry. Apart from her work at IIT, Dr. Shanti Bhattacharya is a Founder Trustee of Chetana Charitable Trust. The Trust seeks to increase awareness on issues of social importance, in particular, Accessible Reading Materials for visually impaired children. In addition to this work, she is an enthusiastic hiker and enjoys many outdoor activities.
02:45PM -- 03:30PM	WES Invited Talk Title: Wireless Network Cloud: A disruptive alternative to conventional network architecture. Abstract: The Wireless Network Cloud (WNC) is a new, disruptive architecture for wireless networks where computational resources for Base Station processing are pooled and provisioned through a central cloud model. Unlike conventional network architecture where dedicated equipment is housed at each cell-tower site, in WNC, these sites have a simple Remote Radio Head (RRH) which sends/receives digitized samples to/from the cloud. Besides the advantages of reduced capex and opex from better resource utilization and more efficient operation, the WNC makes information from multiple base-stations available in a central location. This opens the doors to various base-station co-operation techniques which can greatly improve system capacity by load-balancing, joint signal processing etc. This talk will give an overview of wireless networks as they exist today and the problems they present for telecom service providers; and how the WNC paradigm can be a transformative, long-term solution to a truly flexible, cost-effective and high performance wireless network. Biography: Parul Gupta, IBM Research India Parul received the B.Tech. degree in electrical engineering from the Indian Institute of Technology, Bombay, India, and the M.S. degree in electrical engineering from the University of California, Los Angeles, in 2002 and 2003, respectively. She is currently with IBM Research, Bangalore. She is the technical lead for the Wireless Network Cloud project team in India. Her research interests include everything to do with wireless communication systems, and she has worked on algorithms spanning physical-layer design, Multiple-Input–Multiple-Output (MIMO) systems, medium access control, and cross-layer routing protocols. She is a member of IEEE and ACM, and has co-authored 10 publications and 4 patents. Besides technology, Parul is also very interested in social issues, esp. how technology can be applied in alleviating them. In 2007, she co-founded NGO Post (http://ngopost.org), an online community for sharing development related news and initiatives and facilitating collaboration globally. NGO Post now has a community of 50000+ members and is one of the top-ranking websites in India. Parul received the Foundation of Youth Social Entrepreneurship (FYSE)’s Paragon 100 fellowship for 2009-10 (given to 100 change makers under 30 years of age in the Asia-Pacific region). Parul loves reading and dancing, and spending time with family.
03:30PM -- 04:15PM	WES Invited Talk Title: Learnings from Intel’s Terascale Program Abstract: This talk will cover some of the key learnings from the 80-core Terascale Research processor and its follow-on, the 48-iA core Single Chip Cloud Computer from Intel Labs. These were among the programs which laid the foundation for the launch of a new architecture: the Intel® Many Integrated Core (MIC) architecture targeted for High Performance Computing applications. Biography: Vasantha Erraguntla, Intel Arch. Group, India Vasantha Erraguntla joined Intel’s Teraflop machine design team in 1991 and worked on high-speed router technology. In 1995, she joined Intel’s Design Technology team that was responsible for validating performance verification tools for high-speed designs. Since 1997, Vasantha has been engaged in a variety of advanced prototype designs. As head of Intel Lab’s Bangalore Design Lab, she led the Bangalore team that co-delivered the design of the world’s first programmable Terascale processor and the 48–iA core Single-Chip Cloud Computer. She received 2 Intel Achievement Awards for these designs. Vasantha has co-authored over 13 IEEE journal and conference papers and holds 3 patents and 2 pending. She served on the organizing committee of the 2008 and 2009 International Symposium on Low Power Electronics and Design (ISLPED) and on the Technical Program Committee of ISLPED 2007, Asia Solid State Circuits Conference (A-SSCC) in 2008 and 2009. She is also a Technical Program Committee member for energy-efficient digital design for ISSCC 2010 and ISSCC 2011. She is also serving on the Organizing Committee for the VLSI Design Conference 2011.

DSD-1 : Session Chair: Dr. Saraju Mohanty,

14:  Saraju Mohanty and Elias Kougianos. PVT-Tolerant 7-Transistor SRAM Optimization via Polynomial Regression

1: Varanasi Suresh Kumar and Satyam Mandavilli. Process Variation Tolerant SRAM cell design

42: Ashok Kumar Suhag and Vivek Shrivastava. Delay Testable Enhanced Scan Flip-Flop: DFT for High Fault Coverage

122:  Manisha Pattnaik, Shashank Parashar, Vikas Mahor, Inder Chaudhry and Akanksha Chouhan. A Novel Low Power Noise Tolerant High Performance Dynamic Feed Through Logic Design Technique

DSD-2 : Session Chair: Prof. S.K Nandy, IISc

101:  Alok Baluni, Farhad Merchant, S.K Nandy and S Balakrishnan. A Fully Pipelined Modular Multiple Precision Floating Point Multiplier With Vector Support

13:  Bimal Kumar Meher and Pramod Kumar Meher. A New Look-Up Table Approach for High-Speed Finite Field Multiplication

128:  Prabir Saha, Arindam Banerjee, Partha Bhattacharyya and Anup Dandapat. Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications

12: Ramracksha Tripathi, Shivshankar Mishra and S. G. Prakash. A Novel 14-Transistor Low-Power High-Speed PPM Adder

DSD-3: Session Chair: Prof. D. K. Das

41: Manish Patil, Shaila Subbaraman and Shirish Joshi. Exploring Integrated Circuit Verification Methodology for Verification and Validation of PLC Systems

33: S. Srinivasan, V. Kamakoti and A. Bhattacharya. Towards Improved Solutions for Generalized Placement Problem

117: Manish Baphna. A Method to Reuse RTL Verification tests to validate Cycle Accurate Model

134: Mohammad Hosseinabady, Jimson Mathew, Saraju Mohanty and Dhiraj Pradhan. Single-Event Transient Analysis in High Speed Circuits

DSD-4 : Session Chair: Dr. Smitha K.G, NTU.

60:  Chetan Vudadha, Sai Phaneendra Parlapalli, Syed E, Sreehari V, Moorthy Muthukrishnan N and Srinivas Mb. A Reconfigurable INC/DEC/ 2’s complement/ Priority encoder Circuit with Improved Decision Block

80: K.S. Reddy, M.S. Bharath, Subhendu Kumar Sahoo, Shantanu Sinha and Jaipol Reddy. Design of Low Power, High Performance FIR Filter using Modified Differential Evolution Algorithm

106:  Rakesh V., Smitha K.G. and Vinod A.P.. Low Complexity Flexible Hardware Efficient Decimation Selector

ESD-1 :  Session Chair: Dr. Samrat Sabat

6:  Ramkumar Jayaraman, Handi Kartadihardja and Douglas L. Maskell. Performance-power design space exploration in a hybrid computing platform suitable for mobile applications

45: Harish Yagain and Srinivas Donapati. Addressing the Interoperability Issues While Using JPEG-XR

37:  K.P Karthik, Rangababu P. and Samrat Sabat. System on Chip implementation of Adaptive moving average based multiple-model Kalman filter for denoising Fiber Optic Gyroscope signal

17:  Wei Jhih Wang and Chang Hong Lin. An Improved BitMask Based Code Compression Algorithm for Embedded Systems

ESD-2 : Session Chair: Dr. Hafizur Rahaman

94:  Hemangee Kapoor and Sajeesh K. An Authenticated Encryption based Security Framework for NoC Architectures

46:  Nachiketa Das, Pranab Roy and Hafizur Rahaman. Runtime Congestion and Crosstalk Aware Router for FPGA Using Jbits3.0 for Partial Reconfigurable Application

129:  Pratibha Sawhney, Anup Bhattacharjee and Ganesh. Automatic Construction of Runtime Monitors for FPGA based Designs

130: Naveen Sudhish, Raghavendra Br and Harish Yagain. An efficient method for using Transaction level assertions in a class based verification environment

SSD-1:  Session Chair: Dr. Ranjani Narayan, Morphing Machines, India, ranjani.narayan@morphingmachines.com

72: Parthajit Roy and Jyotsna Kumar Mandal. A Novel Fuzzy-GIS Model based on Delaunay Triangulation to Forecast Facility Locations(FGISFFL)

139: Vishram Mishra, Lau Chiew Tong, Syin Chan and Jimson Mathew. MAC protocol for Two level QoS support in Cognitive Radio Network

20: Jyotsna Kumar Mandal and Somnath Mukhopadhyay. A Novel Variable Mask Median Filter for Removal of Random Valued Impulses in Digital Images(VMM)

68: Nayan Mujaidya. Instruction Scheduling on Variable Latency Functional Units of VLIW Processors

SSD-2:  Session Chair:  Dr. Rajat Gupta, Independent Conultant, India, rajat_gupta@ieee.org

40: Jyotsna Kumar Mandal and Subhankar Ghatak. A Novel Technique for Secret Communication through Optimal Shares using Visual Cryptography (SCOSVC)

87: Jayashree V and Dr Shaila Subbaraman. DCSFPSS Assisted Morphological Approach for Grey Fabric Defect detection and Defect Area Measurement for Fabric Grading

39: Uttam Mondal and Jyotsna Kumar Mandal. A Message embedded Authentication of Songs to Verify Intellectual Property Right(MEAS)

125: Rosario Dhinesh George, Rosario Jagadeesh George and Srikanthan Thambipillai. A Low-Complexity Speaker-and-Word Recognition Application for Resource-Constrained Devices

SSD-3:  Session Chair: Dr. Chandan Haldar, Morphing Machines, India, chandan@acm.org

67: Madhumita Sengupta and Jyotsna Kumar Mandal. Image Authentication using Hough Transform generated Self Signature in DCT based Frequency Domain (IAHTSSDCT)

113: Toshanlal Meenpal and Anup K Bhattacharjee. High Capacity Reversible Data Hiding using IWT

70: Jyotsna Kumar Mandal and Amrita Khamrui. A Data- Hiding Scheme for Digital Image using Pixel Value Differencing (DHPVD)

66: Mohammad Maghsoudloo, Hamid Reza Zarandi and Navid Khoshavi. Low-Cost Software-Implemented Error Detection Technique (Paper will be published, but not presented?)

PSD-1:  Session Chair: Prof. Jacob Abraham, The University of Texas at Austin, USA, jaa@cerc.utexas.edu

140: Satyajeet Nimgaonkar and Mahadevan Gomathisankaran. Energy Efficient Memory Authentication Mechanism in Embedded Systems

38: Aminul Islam, Mohd. Ajmal Kafeel, Ale Imran and Mohd. Hasan. Low Active Power High-Speed Cache Design

62: Mamatha Samson and Satyam Mandavalli. Adiabatic 5T SRAM

124: Priyankar Ghosh, Aritra Hazra, Niraj Bhilegaonkar, Pallab Dasgupta and Chittaranjan Mandal. POWER-SIM : An SOC Simulator for Estimating Power Profiles of Mobile Workloads

PSD-2: Session Chair: Dr. Mahadevan Gomathisankaran, University of North Texas, USA, Mahadevan.Gomathisankaran@unt.edu

84: Chitti Babu B and Samantaray S R. Design and Impementation of Low Power Smart PV Energy System for Portable Applications Using Synchronous Buck Converter

85: Himesh Joshi and Maryam Shojaei Baghini. Versatile Battery Chargers for New Age Batteries

15: Pable S.D, Mohd. Hasan and Mohd. Ajmal Kafeel. Performance analysis of ultralow-power mixed CNT interconnects for scaled technology

AMS-1:  Session chair: Dr Babita, Cochin University of Science and Technology, India

112: Oleg Garitselov, Saraju Mohanty, Elias Kougianos and Priyadarsan Patra. Bee Colony Inspired Metamodeling Based Fast Optimization of a Nano-CMOS PLL

146: Hirak Patangia and Sri Nikhil Gupta Gourisetti. A Harmonically Superior Switching Modulator with Wide Baseband and Real-Time Tunability            

79: Sandeep Goud Surya, Sudip Nag, Sahir Gandhi, Dilip Agarwal, Gaurav Chatterjee and Ramgopal Rao Valipe. Highly Sensitive r/r Measurement System for Nano-electro-mechanical Cantilever based Bio-sensors          

AMS-2:  Session chair: Dr. Dipankar  (email:Dipankar@treelabs.org)

73: Shravan Kumar Karthik, Samrat Sabat and Siba K. Udgata. Performance study of Harmony Search algorithm for analog circuit sizing

93: Mahesh Kumar Adimulam and Srinivas M.B. A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter

132: Manoj Meena, Dipankar - and Rohit Khanna. Nonlinear Inductance Measurement Using an Energy Storage Approach

AMS-3:  Session chair:  Dr. Hafisur Rahman (email: rahaman_h@it.becs.ac.in

133: Rohit Khanna, Dipankar - and Manoj Meena. Design of 0-1KV Controlled Voltage Source

19: Zubair Akhter and Nagendra Pathak. Concurrent Dual-Band Transmitter for 2.4/5.2 GHz Wireless LAN Applications

109: Yalcin Yilmaz and Pinaki Mazumder. Threshold Read Method for Multi-bit Memristive Crossbar Memory

ETD-1:  Session chair: Prof. Bhargab  Bhattacharya , ISI

121: Pranab Roy, Rupam Bhattacharya, Hafizur Rahaman and Parthasarathi Dasgupta. A Best Path Selection Based Parallel Router For DMFBs

9: Hafizur Rahaman and Debaprasad Das. Crosstalk and Gate Oxide Reliability Analysis in Graphene Nanoribbon Interconnects

54: Amrita Som and Amlan Chakrabarti. A New BSQDD Approach for Synthesis of Quantum Circuit

ETD-2:  Session chair: Dr. Narayan Komerath (Email: komerath@gatech.edu)

58: Surajit Kumar Roy, Chandan Giri, Sourav Ghosh and Hafizur Rahaman. Optimization of Test Wrapper for TSV based 3D SOCs

102: Luo Sun, Jimson Mathew and Saraju Mohanty. An Intelligent Statistical Blockade Method for Fast Robustness Estimation and Compensation of Nano-CMOS Arithmetic Circuits

110: Dipak Kole, Hafizur Rahaman, Debesh K Das and Bhargab B. Bhattacharya. Derivation of Automatic Test Set for Detection of Missing Gate Faults in Reversible Circuits

4: Indrajit Pan, Parthasarathi Dasgupta, Hafizur Rahaman and Tuhina Samanta. Ant Colony Optimization Based Droplet Routing Technique in Digital Microfluidic Biochip

ETD-3: Session chair:  Dr. Jimson Mathew (email: jimson@compsci.bristol.ac.uk)               

83: Rajkumar Pant, Narayanan Komerath and Aravinda Kar. Application of Lighter-Than-Air Platforms for Power Beaming, Generation and Communications

57: Surajit Kumar Roy, Chandan Giri, Arnab Chakraborty, Subhro Mukherjee, Hafizur Rahaman and Debesh K. Das. Optimizing Test Architecture for TSV based 3D Stacked ICs using Hard SOCs

123: Bibhash Sen, Mousumi Saha, Divyam Saran and Biplab K Sikdar. Synthesis Of Reversible Universal Logic Around QCA With Online Testability

135: Narayanan Komerath, Aravinda Kar and Rajkumar Pant. Antenna Considerations for Retail Beamed Power Delivery in India